1. Field of the Invention
The present invention relates to an application and development apparatus carrying out an application process of a resist solution on a substrate such as a semiconductor wafer or LCD substrate (glass substrate for liquid crystal display) and a development process after exposure, and a method thereof.
2. Description of the Background Art
There is known a series of steps as a fabrication process of semiconductor devices and LCD substrates, including the steps of forming a resist film on a substrate, exposing the resist film using a photomask, and then applying a development process to obtain the desired pattern. Such a process is conducted employing a system with an exposure apparatus connected to an application and development apparatus that conducts application of a resist solution and development.
The substrate on which a resist pattern is formed is subjected to predetermined inspection such as inspecting the resist pattern line width, the overlapping level between the resist pattern and underlying pattern, development deficiency, and the like. Only substrates passing the inspections are transferred to the next step. Such inspection of substrates is often carried out by a stand-alone inspection apparatus that is provided independent of the application and development apparatus. It would be convenient to employ the so-called in-line system in which a substrate inspection apparatus is provided in the application and development apparatus.
Japanese Patent Laying-Open No. 2002-033266 discloses an application and development apparatus employing such an in-line system. The apparatus includes a carrier block P1, as well as a process block P2 and an interface block P3 connected at the rear side of carrier block P1, and has an exposure apparatus P4 connected to interface block P3, as shown in FIG. 12. Carrier block P1 includes a carrier stage 11 to which a carrier 10 with a plurality of substrates stored therein is transferred, and a delivery arm 12 that transfers a substrate to/from carrier 10 on carrier stage 11. The substrate in carrier 10 is transported to process block P2 via delivery arm 12 to have a resist film formed thereon. Then, the substrate is transferred into exposure apparatus P4 via interface block P3 to be exposed. The substrate subjected to the exposure process is transferred into process block P2 via interface block P3 to be subjected to a development process. The substrate subjected to the development process is transferred to delivery arm 12.
A substrate inspection unit 13 is provided at the side of carrier block P1. The substrate subjected to the development process is transferred by delivery arm 12 into substrate inspection unit 13 via an intermediate stage 15 and a dedicated arm 14 to undergo the aforementioned predetermined inspection. The substrate subjected to inspection is passed to delivery arm 12 through an opposite route to be returned to carrier 10.
If substrate inspection unit 13 is to be connected to a unit other than carrier block P1 (for example, if substrate inspection unit 13 is provided at interface block P3), transportation will become complicated since the substrate subjected to development will be returned to the interface block P3 side, leading to degradation in transportation efficiency. Further, the space to arrange a buffer cassette to absorb the difference in the processing speed from the exposure apparatus, and/or a temperature adjuster unit to set the temperature of the substrate at high accuracy corresponding to the temperature of the exposure apparatus is insufficient in interface block P3. If the substrate inspection unit is arranged, interface block P3 will be increased in size. Provision of substrate inspection unit 13 at process block P2 is inappropriate from the standpoint of space and transportation route.
Thus, substrate inspection unit 13 is connected to carrier block P1. An advantage of this configuration is that, since a substrate can be delivered into substrate inspection unit 13 from an external source via carrier block P1, substrate inspection unit 13 can be used independently even in the case where the application and development process is inhibited due to maintenance or the like at process block P2.
However, this configuration is disadvantageous in that installation in a clean room induces the problem of poor space efficiency since inspection unit 13 will protrude laterally when connected at the side of carrier block P1. The configuration is disadvantageous from the standpoint of arranging peripheral equipment and ensuring space for maintenance. Particularly in the case where a large-sized substrate such as a semiconductor wafer identified as a substrate (referred to as “wafer” hereinafter) that becomes as large as 12 inches or more is involved, the structure in plane of substrate inspection unit 13 will expand to result in a larger protruding area in the lateral direction, which is ever more undesirable.